1. Field of the Invention
The present invention relates to an analog-to-digital converter and, more particularly, to an analog-to-digital converter used in equipment, such as a video signal processor, which requires a high-speed conversion operation.
2. Description of the Related Art
A so-called flush or parallel A/D converter described in literature 1 ("Monolithic Expandable 6 bit 20 MHz CMOS/SOS A/D Converter", ANDREW G. F. DINGWALL, MEMBER, IEEE, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-14, NO. 6, DECEMBER 1979), and a so-called subranging or serial-parallel A/D converter described in literature 2 ("An 8-MHz CMOS Subranging 8-bit A/D Converter", ANDREW G. F. DINGWALL, MEMBER, IEEE, AND VICTOR ZAZZU, MEMBER, IEEE, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-20, NO. 6, DECEMBER 1985) are known typical high-speed A/D (analog-to-digital) converters.
FIG. 4 shows the principle of a parallel A/D converter. An A/D converter converts an analog input signal into an n-bit binary code, and comprises 2.sup.n -1 parallel voltage comparators 10(1) to 10(2.sup.n -1). One input of each comparator commonly receives an analog input signal, and the other input thereof receives reference voltage signals, having different voltage values, generated by reference voltage generator 11. Each voltage comparator 10 compares the voltage value of the analog input signal with the given reference voltage, and supplies the comparison result to encoder 12. Encoder 12 outputs a digital signal corresponding to the comparison results, i.e., an n-bit binary code.
The parallel A/D converter described above can perform very high-speed A/D conversion. However, as can be seen from the above description, a large number of voltage comparators 10, corresponding to the number of quantization steps performed, i.e., 2.sup.n -1, is required for converting an analog signal into an n-bit digital signal. Consequently, this arrangement is quite complex, and an IC chip area required to form the converter is increased in the case of IC formation.
FIG. 5 shows a serial-parallel A/D converter. This converter divides an n-bit binary code into upper a bits and lower b bits, so that A/D conversion relating to the upper a bits is performed by upper-bit A/D conversion section (ADC) 13, after which that relating to the lower b bits is performed by lower-bit A/D conversion section (ADC) 14, on the basis of the conversion result of the upper a bits.
As is shown in FIG. 5, upper-bit A/D conversion section 13 comprises reference voltage generator 11a, voltage comparators 10a, and encoder 12a, in the same manner as the parallel A/D converter shown in FIG. 4. In this case, since A/D conversion corresponding to a bits is performed, the number of voltage comparators 10a provided is 2.sup.a -1. For the same reason as described above, the number of voltage comparators (10b) provided in A/D conversion section 14 is 2.sup.b -1. Thus, the total number of voltage comparators is 2.sup.a -1+2.sup.b -1, and the arrangement can be simpler than that of the parallel A/D converter shown in FIG. 4, which requires 2.sup.n -1 voltage comparators (2.sup.n -1&gt;(2.sup.a -1+2.sup.b -1)).
However, the voltage value of each reference voltage, generated by voltage generator 11b, provided in A/D conversion section 14, is determined by the upper a bit binary code, as the conversion result of A/D conversion section 13. Thus, the conversion operation of A/D conversion section 14 is performed after the conversion in A/D conversion section 13 has been completed. For this reason, A/D conversion sections 13 and 14 cannot execute their conversion operations simultaneously, with the result that the time required to achieve the conversion is doubled as compared to that of the parallel A/D converter shown in FIG. 4.